Forum Discussion

MZama2's avatar
MZama2
Icon for New Contributor rankNew Contributor
6 years ago

Is it possible to monitor LTSSM signals on TEST_OUT bus for PCIe Hard IP?

Hi guys, I was wondering if it is possible to monitor LTSSM signals on TEST_OUT bus. I am using a Cyclone IV GX Transceiver starter kit provided by Altera and have parametrized a PCIe Hard IP in Q...
BoonT_Intel's avatar
BoonT_Intel
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

Hi Sir,

The LTSSM signal is not export to the test_out, thus we can't monitor the LTSSM using test_out bus. Basically, the test_out signal is just a PIPE status signal as describe in this document.

  • MZama2's avatar
    MZama2
    Icon for New Contributor rankNew Contributor
    6 years ago

    Thanks for your comments.

    But what I get from the reference example provided for Cyclone IV GX Tranceiver Starter kit​, it polls test_out[4:0] to detect the transition to L0 state (0x0f). How we can explain this?

    ​