Forum Discussion
AAbro1
New Contributor
New ContributorIs it possible to create an SRAM with Byte Enable and implement it on MLABs(Memory LABs) resources ?
I used the Verilog code below: module Memory(
input we, clk,
input [5:0] waddr, raddr, // address width = 6
input [3:0] be, // 4 bytes per word
input [31:0] wdata, // byte width = 8, 4 bytes pe...
AAbro1New Contributor
New ContributorI tried the solution above and added the ramstyle attribute to force MLAB utilization:
attribute ramstyle : string;
attribute ramstyle of ram : signal is "MLAB, no_rw_check";After compiling I found that fitter used logic LABs resources not MLABs as desired.
Is there any other solution?
