Forum Discussion
AAbro1
New Contributor
New ContributorIs it possible to create an SRAM with Byte Enable and implement it on MLABs(Memory LABs) resources ?
I used the Verilog code below: module Memory(
input we, clk,
input [5:0] waddr, raddr, // address width = 6
input [3:0] be, // 4 bytes per word
input [31:0] wdata, // byte width = 8, 4 bytes pe...
KennyT_altera
Super Contributor
Super ContributorWhat you can do is right click the .vhdl -> insert template.
From there, look for the byte enable template and use it.
Usually, due to different coding style, it would be hard for the Quartus to determined the code to be infer. Let's us know if you still failed to infer after this.
