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Altera_Forum
Honored Contributor
Honored ContributorIP core hardware timeout
Hi, Can anyone out there point me in the right direction so I can add hardware timeout capability to a custom IP core? We plan to generate an IP for a Stratix-IV and would like to have the cu...
Altera_ForumHonored Contributor
Honored ContributorWhat you have described sounds almost exactly like OpenCore method (with time-limited .SOF programming files unless "licensed") and the only way to obtain access to that is through AMPP I believe. My suggestion would be to contact Altera directly and see what they say about your situation.
I guess ideally you would issue your customer an OpenCore unlicensed version they can evaluate with in the lab, and then later issue a non-OpenCore version after they have paid their invoices in order to avoid issuing FlexLM license. Other than that, I think you're looking at rolling your own. I'm not sure you could disable the entire FPGA from your block, but you could certainly make your own block become unresponsive after the timeout.
