IP core hardware timeout

Thanks for the quick response! Please note that our flow is different than the average AMPP partner. Although we do offer fixed functions,

our core business is a design service where we convert c code to VHDL. We typically perform a test run to showcase our capabilities and

report out on the results.

The next step we have in mind is to allow customers to evaluate the test run algorithm on their own hardware platforms. So is there a way we can

add user logic to our IP to program an internal watchdog timer that will shut down (or disable) the FPGA after specified amount of time? Perhaps you

can recommend a better approach if this is not feasible. We are hoping to avoid a licensing scheme. Please excuse my lack of knowledge as my background is with Xilinx.

Thanks,

Jeff