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Michael_B_Intel's avatar
Michael_B_Intel
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6 years ago
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IP Core compile error

Hello, I'm using ATX PLL, PHY IP and IOPLL IP for a proof of concept of a transceiver project. The IP core was successful in generation without any errors/warnings. My VHDL files are without any c...
  • Deshi_Intel's avatar
    Deshi_Intel
    6 years ago
    HI Michael, Is this the Quartus synthesis compilation error ? I can help take a look on the error message if you can attached your quartus design archived QAR. You can also try start build new Quartus project from scratch and see whether the issue still persist or not. Sometime the IP database files may get corrupted and caused error. Thanks. Regards, dlim
Michael_B_Intel's avatar
Michael_B_Intel
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6 years ago

Hi dlim,

Thanks for your answer and your hint!

I created a new project where the issues did not come anymore.

After that I've compared both .qsf files to identify the root cause.

Root cause was the *.ip files where listed as 'VHDL/VERILOG file' and not as IP core file.

Thanks a lot!

This topic can be closed :)

Best regards,

Michael