Forum Discussion
roeekalinsky
Contributor
ContributorIOPLL simulation model pitfall: delta cycle delays vary between clock outputs
The following pertains to the IOPLL simulation models for the Arria 10, Cyclone 10 GX, and Stratix 10, at a minimum (and possibly others I've not yet tested).
I've noticed that the number of delta ...
Ash_R_Altera
Regular Contributor
Regular ContributorWe have received your valuable input for future enhances. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.
