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ADua0's avatar
ADua0
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

Intel opencl read channel stalling

In my opencl design I have 2 channel between 2 kernels,even though design is very simple but I am getting very bad channel stall at the reading side as bad as 99%, even though in my design I do not h...
FawazJ_Altera's avatar
FawazJ_Altera
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

Hello,

Are the kernels connected in a cycle (e.g. k1 writes to k2 and k2 writes to k1)? Or is it purely feed-forward (e.g. k1 writes to k2 via c1 and k1 writes to k2 via c2)? In these situations, it would be good to get the design, compile it, check the reports, and see what things look like. It may be an issue of channel depths or something else in one of the two kernels.

Please send me your design files for further investigation.

Thanks