Forum Discussion
lingxi10
New Contributor
New ContributorIntel FIFO behave differently for M20K and MLAB memory configuration
Hi there,
I am building a project that uses DCFIFO. The write clock comes from PCIe with 125MHz and the read clock comes from PLL with 180MHz. The problem is when I am configuring the FIFO with M2...
Farabi_Altera
Regular Contributor
Regular ContributorHello,
It is recommended for you is to use FIFO IP core generated from Quartus GUI (not from Platform Designer).
Then you can see the generated sdc file for the FIFO IP core and based on the file create your own SDC file for your custom-atom FIFO instances. Please aware that different configuration of FIFO may generate different SDC file.
regards,
Farabi
lingxi10New Contributor
New ContributorI am using the FIFO IP core generated from Quartus GUI. This problem was fixed by selecting the setting to make the aclr of fifo to be synchronized to both read clk and write clk. Thanks for the help
