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User1582192733150209's avatar
User1582192733150209
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6 years ago

Intel FFT IP core timing issue

Hello Sir/Madam, I am simulating the intel FFT IP core, and seems FFT output has some timing issue . Quartus prime pro 17.1 Modelsim-intel starter 10.5c Windows 10 pro Arria10gx FFT con...
tessellation's avatar
tessellation
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6 years ago

I have the exact same issue implementing the FFT with a cyclone V with quartus lite. Although for my implementation i need to pause the FFT stream between packets for 144 clk cycles only. Hence, the solution provided here won't help me.

User1582192733150209's avatar
User1582192733150209
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

Hi tessellation,

thanks for your reply.

I have tried 2 another solution to solve IPG issue for now, both of them not perfect.

solution 1

install 2 FFT core in parallel and switch input packets to 2 fft core alternately, by such arrangement you will not see any IPG issue, IPG can be 0. cost is FFT resource doubled.

solution 2

change output order to digit reverse, then you will not see IPG issue, but cost is you need other logic to do re-order work.

best regard

Jim

  • tessellation's avatar
    tessellation
    Icon for New Contributor rankNew Contributor
    6 years ago

    Thanks Jim, very helpful