New ContributorWhen I create example design for Intel Arria 10Hard IP for PCI Express,I get info as follow:
Error: pcie_a10_hip_0: Unable to generate HDL files for the system pcie_example_design.qsys
Error: Failed to generate example design example_design to: I:\fengran\pcie\pcie_a10_hip_0_example_design
Frequent ContributorHi Sir,
May I know what version that you are using?
I re-try with 18.1 pro edition and I can generate it successfully as below:
Info: The example design example_design was saved to: C:\intelFPGA_pro\18.1\pcie\pcie_a10_hip_0_example_design
Also, did you change any setting on the IP GUI? If yes, I will suggest you retry with default setting and re-generate. the reason is because generated design examples do not cover all possible parameterizations of the PCIe IP Core. If you select an unsupported parameter set, generations fails and provides an error message.
Also, instead of generate the example design, you can get the compiled design from this AN.
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an456.pdf
FPGA programming files for Arria 10 GX FPGA Development Kit for x1 Gen1, x8 Gen2, and x4 Gen3
