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Mingyuexin's avatar
Mingyuexin
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

Instantiating problem when simulating vip test pattern generator

Hi, I'm trying to simulate video processing ip, I do not vip license yet. Anyway, as I understand, it should be able to be simulated even without vip license. I build a simple qsys system with te...
vgs's avatar
vgs
Icon for New Contributor rankNew Contributor
6 years ago

Hi,

The Video processing IP suite is protected with OpenCore Plus. The files generated by Platform Designer in the "synthesis" directory will be encrypted files and your simulation flow is probably incorrect. Platform designer can generate a simulation model for you and these are the files you should be using.

In the platform designer GUI, check the Menu-item Generate > Generate HDL.... > Simulation

Note that it's also possible to do a simulation with a gate-level netlist produced after synthesis and perhaps this is what you are aiming for here (?) but I believe this is not possible with OpenCore Plus if you do not have the full licence.

Kind regards

  • Mingyuexin's avatar
    Mingyuexin
    Icon for Occasional Contributor rankOccasional Contributor
    6 years ago

    Hi,

    Thank you very much for the answer.

    You are right, my simulation flow is not working for this case. I figured out to use to source msim_setup.tcl generated by the tool, the loading problem was solved.

    With best wishes

    Jasmine