Inphase (I) and Quadrature (Q) components of signals

Hi Lee,

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Thanks for the reply. I am trying to compile the testbench, automatically generated by NCO MegaCore function using Quartus 13.1 but an error message:

"Error (10533): VHDL Wait Statement error at ncoIPDesign_tb.vhd(111): Wait Statement must contain condition clause with UNTIL keyword"

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I get a completely different error. Here's what I typed at the Modelsim prompt

cd {C:\temp\alteraforum-leeying}
vlib work
vmap work ./work
vcom -2008 ncoIPDesign.vhd
vcom -2008 ncoIPDesign_tb.vhd
vsim ncoIPDesign_tb

and that produced the following output

#  vsim ncoIPDesign_tb #  Loading std.standard#  Loading std.textio(body)#  Loading ieee.std_logic_1164(body)#  Loading ieee.std_logic_arith(body)#  Loading ieee.std_logic_signed(body)#  Loading work.ncoipdesign_tb(tb)#  Loading work.ncoipdesign(syn)#  ** Warning: (vsim-3473) Component instance "ncoIPDesign_st_inst : ncoIPDesign_st" is not bound.

This error is because the VHDL code you sent does not implement anything. Chances are that the files you posted are for synthesis only - note how the architecture of work.ncoipdesign(syn) is called syn. I would expect the IP to also generate a .vho file for simulation.

You need to re-read the NCO handbook simulation section, it will typically give you instructions on how to simulate a design.

Cheers,

Dave