Inphase (I) and Quadrature (Q) components of signals

Hi Lee,

I/Q demodulation is simply a direct implementation of the Fourier frequency shift theorem, i.e., multiplication by a complex-valued exponential in the time-domain results in a frequency shift in the frequency-domain. The complex-valued exponential can be split into cos + j*sin (Euler's rule), and that is what you implement in hardware.

Take a look at these FPGA-DSP notes for more details ...

http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-104paper_hawkins.pdf

Cheers,

Dave

Hi Dave,

Thank you very much for the document. That is closely related to my project, DDC. I got two questions.

Q1. Does the center frequency of Eq 37 mean the carrier frequency of signals, on page 63 of ESC-104? For example, for 20MHz carrier frequency signals with bandwidth of 1 MHz and sampling frequency 40 MHz, the normalized frequency, fo, will be 20/40. Is it correct?

Q2. Why Eq 37 used -j not +j? Does it matter?

Many Thanks,

Lee

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Q1. Does the center frequency of Eq 37 mean the carrier frequency of signals, on page 63 of ESC-104?

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Yes.

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For example, for 20MHz carrier frequency signals with bandwidth of 1 MHz and sampling frequency 40 MHz, the normalized frequency, fo, will be 20/40. Is it correct?

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That is a special case. Since the carrier is at Nyquist/2 (the center of the sampled band) you do not need an NCO, you can simply use a phasor that rotates 1, -j, -1, j, etc., see slide 117

http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-104slides_hawkins.pdf

The input data to this phase should use a signed-symmetric format, so that the products with -1 or -j do not cause a positive-valued over-flow (or cause 1-bit of bit-growth).

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Q2. Why Eq 37 used -j not +j? Does it matter?

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Inside an FPGA there are two data streams, the real-part Y_I[n] and the imaginary-part Y_Q[n], that complex-valued pair can be represented as (Y_I[n], Y_Q[n]) or equivalently Y_I[n] + j*Y_Q[n]. The quadrature component Y_Q[n] = -sin(2*pi*f0*n), i.e., the negative sign is absorbed into the component, rather than the higher-level representation of the two data streams inside the FPGA.

Cheers,

Dave

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Thanks for the quick reply!

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adding to Dave's response:

If your input is real only, the frequency of mixing can be positive or negative. You get one sideband on zero, the other need filter.

For Fs/2 case I don't see how you can get sin/cos. You only get real frequency.

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For Fs/2 case I don't see how you can get sin/cos. You only get real frequency.

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Sorry, Kaz is right, I misread your 40MHz as the sampled bandwidth, rather than the sampling frequency.

If you are sampling a signal centered on 20MHz at 40MHz clock frequency, then you will likely have aliasing. So you have probably not understood how you need to sample your signal.

As shown in the slides, you can use a NCO at Fs/2 (1, -1, 1, -1, sequence) to flip sidebands, however, that would not apply in your case, since the signal would alias and be corrupted.

Cheers,

Dave

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As shown in the slides, you can use a NCO at Fs/2 (1, -1, 1, -1, sequence) to flip sidebands, however, that would not apply in your case, since the signal would alias and be corrupted.

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Hi Dave,

Can you please explain more about why the signal would alias and be corrupted?

I am trying to replicate the example shown in Figure 36 of your document using "NCO megaCore 13.1 version" but every time I change the 'Desired Output Frequency' value, the Frequency Response plot never changed. I think the version 13.1 NCO has bugs. Have you tried version 13.1 Quartus? I noticed that you used version 12.1 sp1. I might need to use this version instead.

Many Thanks,

Lee

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Can you please explain more about why the signal would alias and be corrupted?

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You stated that your carrier frequency was 20MHz and your sampling frequency was 40MHz. If we assume that your signal of interest is centered on 20MHz and it has some non-zero bandwidth, then if you sample this signal at 40MHz, the Nyquist rate is 20MHz, i.e., the upper-sideband component of the signal will alias on top of the lower-sideband component.

This would be much clearer to you if you created an example for yourself using MATLAB. Eg., you could create a signal sampled at 160MHz, and look at its Fourier transform, then "sample" that signal at 80MHz by keeping every second sample, and look at the Fourier transform, and then "sample" at 40MHz by keeping every forth sample.

But this is starting to get way off-topic, since this forum is really about Altera FPGAs :)

If you have no idea how to create a signal in MATLAB, just ask, and I'll create one for you. Give me an idea of what you need to sample, so that I can create a fake signal that looks similar.

Cheers,

Dave

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I am trying to replicate the example shown in Figure 36 of your document using "NCO megaCore 13.1 version" but every time I change the 'Desired Output Frequency' value, the Frequency Response plot never changed. I think the version 13.1 NCO has bugs. Have you tried version 13.1 Quartus? I noticed that you used version 12.1 sp1. I might need to use this version instead.

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I don't have 13.1 on the machine I am typing on now, I do on my machine at work, along with 14.0, so I'll take a look and write down the steps needed tomorrow.

What FPGA would you like me to target as an example?

Cheers,

Dave