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XCui0
New Contributor
7 years agoInitialization file when infer a RAM IP
Hi, I am using VHDL code to infer a RAM IP of stratix 10. There are two choices to initialize RAM: use a function as provided by the VHDL template, or use attribute as shown in following: type mem_...
XCui0
New Contributor
7 years agoHi SStrell,
Thanks a lot for you recommendation. The problem for the method provided by the link is that the attribute only works inside the scope of generate. That means I need to repeat my generic_ram twice for with init_file and without init_file, and also I have to declare my data type and ram signal inside the generation, twice. My code is pretty long now, because I have all ram function in one file, such as single/dual port, single/dual clock, with/without byte enable, mixed ports or non mixed ports. Upper level uses different generic settings to choose the function of ram. So, it seems not a good solution for me. Thank you anyway. Please let me know if you have other ideas.
Thanks,
Xin