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XCui0
New Contributor
New ContributorInitialization file when infer a RAM IP
Hi, I am using VHDL code to infer a RAM IP of stratix 10. There are two choices to initialize RAM: use a function as provided by the VHDL template, or use attribute as shown in following: type mem_...
sstrell
Super Contributor
Super ContributorThe only thing I can think of would be if you could make the attribute conditional. Google brought up this though it's not clear if it works or not and I don't know if it would synthesize in Quartus:
https://stackoverflow.com/questions/17492197/vhdl-conditional-attribute-declaration-depending-on-a-generic
That might give you a starting point.
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