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Andy1's avatar
Andy1
Icon for New Contributor rankNew Contributor
6 years ago

Inferred Latches in CVI II core with Quartus Pro v18.1

Hi, There are currently 2 warning in the synthesis report for the CVI II VIP core: Warning(16864): Verilog HDL warning at alt_vip_cvi_av_st_output.sv(283): arg0 may be used uninitialized in static...
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi Andy,

Based on my understanding, these warnings can be ignored due to optimization. Just would like to check with you if you observe any issue running your design in simulation and hardware with CVI II?

Please let me know if there is any concern. Thank you.