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AVija7's avatar
AVija7
Icon for New Contributor rankNew Contributor
6 years ago

Incorrect data at rx_dataout of stratix IV

Sir i designed the code for TX and RX using ALTGX,ALTRECONFIG in stratix IV. And successful at loopbacking, chip to chip communication.etc. In real case we have transmitter designed by someone else....
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi,

As I understand it, your latest observation seems to be related to byte ordering issue. Would you mind to further elaborate on why you are unable to enable the byte ordering block?

Probably you can share with me your .ip or .qsys file of the Native PHY so that I can have a better understand of your configuration to further advice.

Thank you.