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AVija7's avatar
AVija7
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6 years ago

Incorrect data at rx_dataout of stratix IV

Sir i designed the code for TX and RX using ALTGX,ALTRECONFIG in stratix IV. And successful at loopbacking, chip to chip communication.etc. In real case we have transmitter designed by someone else....
AVija7's avatar
AVija7
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6 years ago

Sir,

I was able to receive the proper data, but with reverse order.

Earlier problem solved by providing the correct values for LOCK TO DATA, LOCK TO REF inputs.

Problem facing now:

I wanted to receive BC95B5B5 but receiving B5B595BC.

This happened when i gave "Word aligner pattern : 17C (K28.5)---10 BIT"

When i gave BCBC (5F17C) as control code, i lost sync

not only that im not sure about the exact control code.

For 10 bit we cant enable byte ordering block.

How to proceed sir??

Thanks and regards.