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AVija7's avatar
AVija7
Icon for New Contributor rankNew Contributor
6 years ago

Incorrect data at rx_dataout of stratix IV

Sir i designed the code for TX and RX using ALTGX,ALTRECONFIG in stratix IV. And successful at loopbacking, chip to chip communication.etc. In real case we have transmitter designed by someone else....
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi,

As I understand it, you are observing the rx_errdetect and rx_disperr seems to be toggling while the sync status remains high. For your information, this seems to indicate that there are 8b10b errors detected at the received data. To facilitate further debugging, just would like to check with you if you have had a chance to tap rx_pll_locked and rx_freqlocked signals in signaltap? This will be helpful to tell if the CDR still remain locking to data or has already lost lock.

In addition, signal integrity issue might lead to the 8b10b errors that you are observing. Just wonder if you have had a chance to check on the eye diagram at the SIV RX ball to see if it is still meeting RX spec in datasheet?

Please let me know if there is any concern. Thank you.