Forum Discussion
IOzan
Occasional Contributor
Occasional ContributorIn the SCFIFO simulation , after asserting the sclr signal, the q output of the SCFIFO is set to X', Why is that?
As documented in the SCFIFO and DCFIFO Megafunction User Guide (PDF), after assertion of the sclr signal, the q output should maintain the last value or display the first data word for SCFIFO.
AnandRaj_S_Intel
Regular Contributor
Regular ContributorHi @IOzan ,
Can you attache your simulation image?
Yes,
When sclr is asserted, the FIFO megafunction is immediately reset,
■ The q[] port flushes the first data in the FIFO on the immediate rising clock edge
■ All rdreq and wrreq signals are ignored (as long as the sclr signal remains asserted)
When aclr is asserted, the FIFO megafunction is immediately reset,
■ The q[] output is cleared
■ All rdreq and wrreq signals are ignored (as long as the aclr signal remains asserted)
Refer below image
Regards
Anand
