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alinave's avatar
alinave
Icon for New Contributor rankNew Contributor
6 years ago

In the Low Latency 100G Ethernet Intel®Stratix® 10 FPGA IP Core, can one of the two ATX PLLs be used as a clock buffer?

The Low Latency 100G Ethernet Intel®Stratix® 10 FPGA IP Core user guide suggest that the input reference clock pin to the ATX PLL must be a dedicated reference clock pin (2.4.2. Adding the Transceive...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

HI Naved,

Just want to close loop with you on this issue to set this case to closure since the ATX PLL usage model has been clarified.

For now, I am setting this case to closure.

Thanks.

Regards,

dlim