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alinave's avatar
alinave
Icon for New Contributor rankNew Contributor
6 years ago

In the Low Latency 100G Ethernet Intel®Stratix® 10 FPGA IP Core, can one of the two ATX PLLs be used as a clock buffer?

The Low Latency 100G Ethernet Intel®Stratix® 10 FPGA IP Core user guide suggest that the input reference clock pin to the ATX PLL must be a dedicated reference clock pin (2.4.2. Adding the Transceive...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

HI,

Yes, it can be used as clock buffer.

For reference, you can always generate the 100G example design directly from the IP core to review the design connection.

This is a better way to clarify issue rather than read through the doc.

Thanks.

Regards,

dlim

alinave's avatar
alinave
Icon for New Contributor rankNew Contributor
6 years ago

Hi dlim,

Thanks for checking. It was not used as a buffer in the example design. Hence I wanted to confirm.

Thanks,

Naved