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alinave's avatar
alinave
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6 years ago

In the Low Latency 100G Ethernet Intel®Stratix® 10 FPGA IP Core, can one of the two ATX PLLs be used as a clock buffer?

The Low Latency 100G Ethernet Intel®Stratix® 10 FPGA IP Core user guide suggest that the input reference clock pin to the ATX PLL must be a dedicated reference clock pin (2.4.2. Adding the Transceive...
Rahul_S_Intel1's avatar
Rahul_S_Intel1
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6 years ago

Hi ,

I am expertise in PLL , let me check the expert in Ethernet / Transceiver and will get back to you.

  • alinave's avatar
    alinave
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    6 years ago

    Hi @RahulS_Intel​ ,

    That would be great help! Much appreciated.

    -Naved