In the Low Latency 100G Ethernet Intel®Stratix® 10 FPGA IP Core, can one of the two ATX PLLs be used as a clock buffer?

Hi RSree,

Thanks for the reply. It would need two ATX PLLs for sure. But can one of them act as a transmit PLL to clock two GXT channels while other is being used as a clock buffer to clock the other two channels? This is shown in Figure 4.PLL Configuration Example where one of the ATX PLL is shown as a buffer.

The clock network which I am referring to is also shown in Figure 141.Main and Adjacent ATX PLL IP Instances to Drive 6 GXT Channels of

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/stratix-10/ug_stratix10_l_htile_xcvr_phy.pdf

Thanks