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alinave
New Contributor
New ContributorIn the Low Latency 100G Ethernet Intel®Stratix® 10 FPGA IP Core, can one of the two ATX PLLs be used as a clock buffer?
The Low Latency 100G Ethernet Intel®Stratix® 10 FPGA IP Core user guide suggest that the input reference clock pin to the ATX PLL must be a dedicated reference clock pin (2.4.2. Adding the Transceive...
Rahul_S_Intel1
Frequent Contributor
Frequent ContributorHi ,
As mentioned in the user guide , in the Low Latency 100G Ethernet , have to use two ATX PLL.
alinaveHi RSree,
Thanks for the reply. It would need two ATX PLLs for sure. But can one of them act as a transmit PLL to clock two GXT channels while other is being used as a clock buffer to clock the other two channels? This is shown in Figure 4.PLL Configuration Example where one of the ATX PLL is shown as a buffer.
The clock network which I am referring to is also shown in Figure 141.Main and Adjacent ATX PLL IP Instances to Drive 6 GXT Channels of
Thanks
- alinave
