Forum Discussion
JHaye4
Occasional Contributor
Occasional ContributorIllegal Connection with GPIO Intel® FPGA IP output buffer.
I am using the GPIO Intel® FPGA IP core to connect a Intel FPGA Avalon I2C (Master) Core to the pins of my FPGA.
When I connect the "dout" port of the buffer in bidirectional mode to my core logic ...
JHaye4Occasional Contributor
Occasional ContributorResolved by not being silly and connecting ports correct way round.
