Forum Discussion

WQIUS's avatar
WQIUS
Icon for New Contributor rankNew Contributor
7 years ago

I use the FPGA of cyclone V which type is 5CGXFC3B7F23C8N ,which has 1 GXB Bank （3 transceiver channel）,CH0/CH1/CH2，but CH1 has error

I download the design example “cv_GX_1ch_40b_3125mbps”，change the chip to mine（ 5CGXFC3B7F23C8N），the Channel 1 has error，how can I do？
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
7 years ago

​Hi WQIUS,

Sorry for the delay. For your information, I have downloaded the cv_GX_1ch_40b_3125mbps.qar and tried to perform compilation in Q17.0 (since I do not have Q18.0 installed currently in my PC). After performing the auto-upgrade for IPs, removed all pin assignment as well as changing the parts to 5CGXFC3B7F23C8, I get into other Fitter errors which are different from yours. They are mainly related to unsupported PHY configuration and data rate. After fixing these errors, I am able to compile the design without Fitter error. Would you mind to share with me what are the changes that you have done to the cv_GX_1ch_40b_3125mbps.qar which would lead to your observation? This would be helpful for issue replication and further debugging.

Thank you.

Best regards,

Chee Pin