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HBhat2's avatar
HBhat2
Icon for Contributor rankContributor
7 years ago

How to send Electrical IDLE in transceiver lines?

Hi, Using Stratix 10 Native PHY IP, I am interfacing to custom PCIe Logic and custom PCS to transmit PCIe like traffic using transceiver lanes. Here, I have some concerns on Electrical IDLE. 1) As...
SengKok_L_Intel's avatar
SengKok_L_Intel
Icon for Regular Contributor rankRegular Contributor
7 years ago
Hi HPB, Below are my answer: 1. As per the PCIe Spec, to enter the ELECTRICAL IDLE stage, the link partner is required to send the EISO( Electrical Idle Order Set), and it can't achieve if somehow the transmitter FIFO is empty. 2. Exist from the Electrical Idle, the transceiver does not require to perform re-calibration but the word alignment has to re-run. Regards -SK
  • HBhat2's avatar
    HBhat2
    Icon for Contributor rankContributor
    6 years ago

    Hi @SengKokL_Intel​ ,

    1) As I understand the spec, in electrical IDLE state, the common mode voltage shall be maintained in the serial lines. So, with respect to S-10 transceiver, in what way I can maintain common mode voltage in the transceiver serial line, but no toggling.

    2) "the transceiver does not require to perform re-calibration but the word alignment has to re-run. " Now I understand and agree with this statement.

    With Regards,

    HPB