Forum Discussion
New ContributorHow to map TX Avalon-MM slave interface into PC virtual memory?
Hi Eduardo,
No, the TXS port should connect to your application interface NOT BAR.
If the read/write request is initiated from your application via TXS port to the host, and then the host will be responding to those requests accordingly.
The size of the host system memory can be 32 bits (2 ^32) or maybe 64 bits (2^64), you will need to confirm it from your host system.
It depends on which locations of the system memory that you would like to read/write from FPGA. In the IP GUI, there is an address translator table for you to fill in, and this is up to the user to decide where the system memory that their design need to access.
Regards -SK
Regular ContributorHi,
BAR0 is AVMM master port, this is for host to access the endpoint (Host -> FPGA), where host issue read/write command, and FPGA response on it.
The TXS port is AVMM slave, this is for End point to access host (FPGA -> Host) where endpoint issue memory read/write command, and host response on it. The address width of the TXS depends on the setting of the size of address Page.
Regards -SK
EPinoGot it!
So the problem is: How do I know where in host memory will TXS write to?
Should I map host memory into the FPGA?
Regards,
Eduardo
