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DHUAN26's avatar
DHUAN26
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7 years ago

How to initialize the Configuration Space when PCIe core in Root port mode?

I can read Device id and Vendor id of Root Port, but can not read Device id and Vendor id of Endpoint by user logic. PCIe core connect with only one Endpoint,and only one lane.
RWitt's avatar
RWitt
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7 years ago

DHUAN26 - did you get any further? By the way - in one of your examples above remember that the register is shifted two bits in the config header, just a warning.

I'm trying to write the 0x18 register of the Arria-10 RootPort, with a value 00010100 - so the downstream bus would be 1, subordinate bus 1 (only one bus downstream). The write occurs to the RP on the Avalon bus, the RP responds with a status = success, but when I read that register I always get back 00s. Like DHUAN - I can read the dev-id (info configured in Platform Designer), I just can't write anything through the ST interface.

Anyone have success doing that?

I'm guessing I could move the config-space registers external, or use the LMI, but before that - this TLP method on the ST interface is supposed to work.

Regards,

Bob