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DHUAN26's avatar
DHUAN26
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7 years ago

How to initialize the Configuration Space when PCIe core in Root port mode?

I can read Device id and Vendor id of Root Port, but can not read Device id and Vendor id of Endpoint by user logic. PCIe core connect with only one Endpoint,and only one lane.
Nathan_R_Intel's avatar
Nathan_R_Intel
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7 years ago

Hie,

There could be various reasons why you cannot get a TLP reply from a EP. Hence, you will need to debug further. I believe you are currently following our user guide recommendation that before you issue transactions to the Endpoint, you must configure the Root Port and Endpoint Configuration Space registers.

I am sorry, it is diffcult to understand what your trying to enable using the CfgWr0. Hence, I don't have enough information to advice on this. As for using the Config Type 0 write Request, you could refer to our user guide on the rules.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_a10_pcie_avst.pdf

Regards,

Nathan