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Altera_Forum's avatar
Altera_Forum
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11 years ago

How to handle complex external signals in Qsys

It seems that in Qsys, it is not possible to export any signal that is not STD_LOGIC or STD_LOGIC_VECTOR (or a SUBTYPE thereof). Is this correct ? We have a slave that exports a bunch of these ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Right, Qsys only handles std_logic or std_logic_vector. This basically stems from the fact that Qsys (and SOPC) is 'Verilog' (which doesn't have a 'record' construct).

I code 'to_std_logic_vector( r_type : r)' and 'to_r_type( v : std_logic_vector)' functions for every record I create. The record definition has to go in a package anyway, so including the two functions makes connecting Qsys components easy.