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minjoolee's avatar
minjoolee
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4 years ago

How to generate ALLPLL in S10 ?

Hi, I am tried to converter old pll in quartus 13.1 to quartus pro 21.x OLD ALLPLT has scanclk/scandataout port from tool . // synopsys translate_off `timescale 1 ps / 1 ps // sy...
minjoolee's avatar
minjoolee
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4 years ago

I know that I have to generate,

but how to do for ALLPLL.

in IOLL itel FPGA IP from quatur pro,

doesn't have

scanclk,
scanclkena,
scandata,

these pins.

That is why I don't re-generation.