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Altera_Forum
Honored Contributor
12 years agoHi,
thank you for your response. @Cris72: That's a quite simple trick :) and it would work, as the synthesis tool is optimazing all unconnected components. The problem is to set these reset signals to a determindet value due to the instance parameter set. Currently I am using this kind of trick in my "long-winding solution", since I disable the interfaces of the unused components. @Dave: Fortunately I have not to simulate the IP-Cores. As I interpret your recommendation, you are using a tcl-file to describe your top-level instance, right? And the top-level consists of several filesets containing VHDL-designs and simulation information. Again these filesets will be modified in the fileset_callback procedure according to the users choice. Krgds MrFreshman