how to ENABLE/DISABLE parts of an IP-core depending on the instance parameters??

I'd suggest this simple trick, although I'm not sure it works.

Use distinct reset signals for the A and B blocks and export them out of Qsys core.

In the fpga design using the core, hardwire the reset port of the component you don't want to use (let's say B), while connecting the other one (block A reset) to the true reset signal.

This way I think the synthesizer would trim away all logic related to block B which won't be implemented, as if it had been disabled in Qsys.

Do the opposite in case you'd like to use block A.