How to debug the FFT IP using a custom made test-bench according to the user requirements using a vhdl test-bench in quartus 16.1.2 ??

Hi,

To configure Quartus to use Altera-Modelsim as the simulator go to Assignments > Settings > EDA Tool Settings > Simulation Make sure “Modelsim-Altera” is selected as the tool Next go to Tools > Options > General > EDA Tools sure that the path next to ModelsimAltera is configured correctly (example path=C:\altera\13.0sp1\mode-sim_ase\win32aloem)

1. We have to write the testbench in HDL.
2. Since you are using IP we should use the scripts(msim_setup.tcl) to load the libraries or supporting files.
3. The Quartus® Prime software generates simulation files for each IP core during IP generation,The IP generation output also includes scripts to compile and run any testbench.

In your FFT design you can find msim_setup.tcl file read the file which will help you in simulating.create a simple scrtip including your IP msim_srtup & testbench.vhd.

It should look like

set QSYS_SIMDIR C:/Users/anandr1x/Desktop/fftpro
source mentor/msim_setup.tcl 
#dev_com 
# Override the top-level name (so that elab is useful)
set TOP_LEVEL_NAME fftprotb
# Compile the standalone IP.
com
# Compile the user top-level vlog -sv ../../top.sv
vlog -sv fftprotb.v
# Elaborate the design.
elab

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

Regards

Anand