Forum Discussion

MDehp's avatar
MDehp
Icon for New Contributor rankNew Contributor
7 years ago

How to connect PLL clock to second Triple-Speed Ethernet MAC?

Hi guys, I have set up a design with two TSE MAC's, the design already works in simulation. Now I want to test the design on my MAX10 FPGA, but I can't figure out how to connect the second TSE MAC ...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
7 years ago
Hi Mansur, It's recommended to configure the PHY chip as I don't think it will auto configured by itself. Normally the register mapping should be in the PHY chip datasheet. You can contact the PHY chip vendor if you required further technical support or clarification. Thanks. Regards, dlim