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MDehp's avatar
MDehp
Icon for New Contributor rankNew Contributor
7 years ago

How to connect PLL clock to second Triple-Speed Ethernet MAC?

Hi guys, I have set up a design with two TSE MAC's, the design already works in simulation. Now I want to test the design on my MAX10 FPGA, but I can't figure out how to connect the second TSE MAC ...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
7 years ago
Hi Mansur, Yes, you have the option to either enable or disable MDIO in TSE IP in RGMII mode. MDIO is a common interface where we use to configure external PHY register setting. However, if your external PHY chip has other method to configure the register setting then go ahead to disable MDIO else pls stick to MDIO. Thanks. Regards, dlim
MDehp's avatar
MDehp
Icon for New Contributor rankNew Contributor
7 years ago

Hi dlm,

My FPGA uses 2x the 88E1111 PHY chip. Is it a must that I configure the MDIO registers, or are they configured automatically if I turn off both MDIO of the TSE IP?

Because I can't find the register mapping of the PHY chip.

Regards,

Mansur