Forum Discussion
MDehp
New Contributor
New ContributorHow to connect PLL clock to second Triple-Speed Ethernet MAC?
Hi guys, I have set up a design with two TSE MAC's, the design already works in simulation. Now I want to test the design on my MAX10 FPGA, but I can't figure out how to connect the second TSE MAC ...
Deshi_Intel
Regular Contributor
Regular ContributorHi Mansur Dehpoor,
You can check out TSE user guide doc chapter 7 : Design consideration (page 142)
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_ethernet.pdf
It's ok to use same clock source for multiple MAC instance.
Thanks.
Regards,
dlim
MDehpThanks for your reply.
I have another question concerning the MDIO interface.
Do you know if I could leave out the MDIO interface of both TSE MAC's in RGMII mode?
Or do I need to configure the PHY registers through the MDIO interface. (enable/disbale auto-negotiation?)
For now I have disabled the MDIO option for both MAC, but data transfer between the two MAC's isn't realized yet.
