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MDehp's avatar
MDehp
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7 years ago

How to connect PLL clock to second Triple-Speed Ethernet MAC?

Hi guys, I have set up a design with two TSE MAC's, the design already works in simulation. Now I want to test the design on my MAX10 FPGA, but I can't figure out how to connect the second TSE MAC ...
  • MDehp's avatar
    MDehp
    Icon for New Contributor rankNew Contributor
    7 years ago

    Thanks for your reply.

    I have another question concerning the MDIO interface.

    Do you know if I could leave out the MDIO interface of both TSE MAC's in RGMII mode?

    Or do I need to configure the PHY registers through the MDIO interface. (enable/disbale auto-negotiation?)

    For now I have disabled the MDIO option for both MAC, but data transfer between the two MAC's isn't realized yet.