Forum Discussion

YYang79's avatar
YYang79
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

How to clock the Cyclone 10GX Transceiver Channel for 10GBASE-R

Hi, In “Intel® Cyclone® 10 GX Transceiver PHY User Guide” at page 100, Fig.44, the tx_clkout is 322.265625 Mhz when select PMA bus width of 32 bits (in picture, it says a number for 40 bit wide bus...
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


As I understand it, you have some inquiries related to the clocking for the C10GX 10GBaseR. For your information, you should connect the tx_coreclkin with XGMII clock of 156.25MHz. I believe there might be some typo in the user guide or some of the internal blocks are not shown. Sorry for the inconvenience. However, at the top level, you would need to 156.25MHz to tx_coreclkin.


To further validate your design, it is recommended for you to create a simple test design and run through simulation to check for basic functionality before you add in more module.


Please let me know if there is any concern. Thank you.


  • YYang79's avatar
    YYang79
    Icon for Occasional Contributor rankOccasional Contributor
    5 years ago

    Hi,

    In my whole system, the receiver's phy-layer is a TI's TLK10031 which is a 10BASE-KR chip. My transmitter is a Cyclone 10 10BASE-R transceiver. Do you think it is workable together?

    I found the receiving data with missing 64-bit words frequently at receiver's XGMII bus monitored by SignalTap.

    Looking forward to your help.