Forum Discussion

SSmit7's avatar
SSmit7
Icon for New Contributor rankNew Contributor
6 years ago
Solved

How to activate loopback mode for debugging Cyclone V GX PCIe link

Hello I am using the PCIe-to-Avalon-MM Hard IP core in a 5CGXFC3B6U19I7 device, and I would like to enable loopback mode to debug the link between the FPGA and the processor that I am using. The FP...
  • SengKok_L_Intel's avatar
    SengKok_L_Intel
    6 years ago

    Hi,


    To achieve the loopback mode at the endpoint, the host may act as a loopback master, and send two consecutive TS1s with loopback bit set, so that the endpoint can enter the loopback mode. You may refer to the PCIe spec for the detailed information.


    Regards -SK


srinivasan's avatar
srinivasan
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Hi,

Facing same problem in the design,Please suggest how to set that consecutive TS1 loopback bit in the root complex design....

or

Please share the root complex loop back reference design.