How the data is transferred by TX port of Avalon-MM PCIe

Hi,

The TX Avalon-MM slave port of Avalon-MM Cyclone V Hard IP core has burst capabilities. The TxsBurstCount signal allows bursts limited to 512 B.

My questions are related to how the V PCIe core translates write requests from interconnect fabric into PCI Express memory write packets. The fabric as a bursting Avalon-MM master is connected to the slave TX port. The master sets starting addres and burst count at the beginning of Avalon transfer. Next data are written until the end of this burst. It is expected that the data will be sent in PCIe memory write packet.

The PCI Express TLP header has 'Length' field specifying the length of data payload. According to PCI Express specification, TLP payload size can be less or equals to the maximum value.

It is important when PCIe packet is generated with reference to the end of Avalon burst write.

If FPGA fabric want to write e.g. 64 bytes of data, which is less than the maximum value for TLP data payload, it can generate one Avalon-MM write transfer with burst count for 64 bytes? No padding is required?