How exactly does the rx_std_signaldetect work in the Cyclone V

Hi, As I understand it, you have some inquiries related to the rx_std_signaldetect output port. Generally this signal will be asserted when the incoming signal meet a certain set of thresholds that you set. Also, please note that the signal detect circuitry requires input data stream to be 8b10b coded. In other words, you would need to enable the 8b10b blocks as well. As a quick start, you may refer to the V-Series Trasnceiver PHY IP Core User Guide -> "Table 16-15: Bit Reversal and Polarity Inversion Parameters" -> "Enable rx_std_signaldetect port" for the QSF assignments required for SATA/SAS application as example and try if it works for you. The following are the example from user guide for your reference: set_instance_assignment -name XCVR_RX_SD_ENABLE ON set_instance_assignment -name XCVR_RX_SD_THRESHOLD 7 set_instance_assignment -name XCVR_RX_COMMON_MODE_VOLTAGE VTT_OP55V set_instance_assignment -name XCVR_RX_SD_OFF 1 set_instance_assignment -name XCVR_RX_SD_ON 2 Please let me know if there is any concern. Thank you. Best regards, Chee Pin

Hi, Just would like to follow up with you on this. Thank you.

Sure, please feel free to keep me posted. Thank you.

Hi, Just would like to follow up with you on this. thank you.