Forum Discussion
Occasional ContributorHow effective is the video Frame Buffer core when storing in memory?
The information is in document ""Video and Image Processing Suite User Guide (UG-VIPSUITE | 2021.02.12)" section "16.7.3. Memory Map for Frame Reader or Writer Configurations" paragraph "The frame data is tightly packed into memory and aligned on frame (or field) boundaries to minimize storage usage and maximize memory bandwidth usage."
So the data is tightly packed in memory.
Frequent ContributorHi MoZdk,
Usually memory bandwidth(efficiency) is 90% with increment address, but bandwith will drop to 50% with random address.
May I know the memory interface Avalon clock frequency and video stream Avalon clock frequency?
Best Regards,
Zul
MoZdkHi Zul,
The frequencies are pretty moderate with DDR3 at 400 MHz and video pipe at 112.5 MHz in a Cyclone V device, with pixel rate of 2 per cycle.
As I noted, the question was answered based on the reference I made above, with information about how the VFB stores data on the Avalon-MM IF. That will be linear, but for best efficiency then Bank-Row-Column mode must be used in the DDR3, with frame spacing that ensure different frames goes in different banks, to benefit from open row on both write and read side of the VFB.
Best regards MoZdk
