How do i use E-Tile Transceiver Native PHY Intel Agilex FPGA IP?

Question

I tried to connect my own MAC ip with the E-Tile Transceiver Native PHY Intel Agilex FPGA IP.But only tx channnel works correctly.The rx data did not meet expectations.

If i connect the MAC PMA tx data to MAC PMA rx data,the mac IP works correctly,So i suspect a problem with the serdes IP configuration.I have read the use guide bug still can't find the problem.

I don't know how to locate the problem.Can you give me an example design with 25G，2 eth port.

My quartus version is 22.4,Device is Agilex:AGFB027R25A2E3E.

ziying_intel · Answer

Hi,For further information about 25G 2 port design, you may refer to link below, https://www.rocketboards.org/foswiki/Projects/Agilex7SoCFTileDesignExampleWithIEEE1588PTP25GEBest regards,zying

kokodo · Answer

I want an E-Tile Transceiver Native PHY Intel Agilex FPGA IP,not F-Tile

ziying_intel · Answer

Hi,I only found this 25G E-tile example design. For further information about 25G E-tile example design, please do refer to the link below, https://www.rocketboards.org/foswiki/Projects/AgilexSoCETileDesignExampleFor25GbeWithIEEE1588PTPSustainingBest regards,zying

ziying_intel · Answer

Hi,Since no hear any feedback from you, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread.Best regards,zying

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How do i use E-Tile Transceiver Native PHY Intel Agilex FPGA IP?

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