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KMich2's avatar
KMich2
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6 years ago

How do I select which hard memory controller to use if my FPGA has two controllers?

I am using an Arria V GX which is suppose to have 2 hard memory controllers. How do I select which one to activate as the UNIPHY memory controller seems to only work with bank 7 but my memory device ...
NurAida_A_Intel's avatar
NurAida_A_Intel
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6 years ago

Hi KMich2,

The Arria V HMC use dedicated I/O pins as data, address, command, control, clock, and ground pins for the SDRAM interface. I have highlighted the hard memory interface pin-out in YELLOW in attached pin-out excel file. Therefore, user shouldn’t be assigning hard memory interface DDR3 pin-out to other pin location anymore. Only dedicated pin-out is acceptable.

I suggest you to modified your design by removing all the pin location assignment for DDR3 IP and re-compile your project.

Hope this helps.

Thanks

Regards,

NAli1

  • KMich2's avatar
    KMich2
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    6 years ago

    The pin assignments we are using are in accordance to this table, but for the hard memory controller pins shown on IO bank 4, instead of IO bank 7 (which are automatically assigned by the fitter if we do not constrain the pins). As there are two hard memory controller, how do we get the fitter to use the other one, as our memory chip is wired to IO bank 4 and changing our design is not an option for us.

  • KMich2's avatar
    KMich2
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    6 years ago

    Another question related to this table... How do we invoke the 'optional function' on a pin, for example the VREFB4DN0 on pin AA12. I understand this should be an externally supplied reference voltage for bank 4D at 1/2 the selected IO standard for the bank, but the pin also seems to serve as an IO pin. Do we need to configure the pin to use it as a voltage reference input?

    • NurAida_A_Intel's avatar
      NurAida_A_Intel
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      6 years ago

      Hi KMich2,

      Depending on your design, if you used verilog code then you can set the input pin in your RTL ( as shown in Figure 1) , re-compile the design ( compile at Analysis and Synthesis stage will do) and assign this PIN_AA12 as input in your Pin Planner (Figure 2). Then directly connect the VREF to this PIN_AA12. Make sure also the I/O standard is set accordingly with your design. What shown in Figure below is just an example for your reference. 😊

      Figure 1:

      Figure 2:

      If you are using the Qsys, then set the input in Qsys.

      Hope this helps.

      Thanks

      Regards,

      NAli1

    • KMich2's avatar
      KMich2
      Icon for New Contributor rankNew Contributor
      6 years ago

      OK, so I just need to assign the pin as an input and it will act as a reference for all the other pins on the bank? Thanks.

    • NurAida_A_Intel's avatar
      NurAida_A_Intel
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      6 years ago

      ​Yes , you are right.

      You are most welcome 😊

      Regards,

      NAli1