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JDESC3
New Contributor
New ContributorHow do I configure a PCIe Root Port?
I am trying to follow the example in the Intel® Arria® 10 and Intel® Cyclone® 10 GX Avalon®-MM Interface for PCI Express* User Guide 6.8.3 “Examples of Reading and Writing BAR0 Using the CRA Interfa...
JDESC3New Contributor
New ContributorAfter following the link you provided to the FPGA Design Tools Forum, "FPGA Design Tools" is not one of the options in the "Post To" drop down box when posting questions.
FPGA Intellectual Property was the closest category I found.
Please elaborate on where you would like me to post this question about the PCI Express IP core.
