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MEmel1's avatar
MEmel1
Icon for New Contributor rankNew Contributor
6 years ago

How can I initiate burst transfer for Avalon-MM in EMIF Cyclone 10?

Hello, My problem is that the component altera_emif_c10 (DDR3) doesn't complete reads with burstcount[..] set to more than 1. According to Avalon-MM interface protocol burst writes and reads are co...
NurAida_A_Intel's avatar
NurAida_A_Intel
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

Dear MEmel1,

The burstbegin signal is redundant. When the amm_write start issue write request signal and it start to initiate the burst begin signal. And user can control the burst by setting the burst count.

You may want to try run simulation on the example design to get clearer picture on the timing diagrams and how the signal operate on the example design.

Hope this helps.

Thanks

Regards,

NAli1