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MEmel1
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6 years ago

How can I initiate burst transfer for Avalon-MM in EMIF Cyclone 10?

Hello, My problem is that the component altera_emif_c10 (DDR3) doesn't complete reads with burstcount[..] set to more than 1. According to Avalon-MM interface protocol burst writes and reads are co...
MEmel1's avatar
MEmel1
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6 years ago

Yes, there should be burstbegin signal according to the documentation you provided. But it's not present in my component schematic. May be there's also an oprion to make it visible?